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| January 1998 Features S IG N DES EW t RN ter a D FO 1 Cen sc DE 17 ort t EN MM ee HI1 l Supp il.com/ S ni c a ECO rs R te h w .in N OT Te c High ou r L or w w t SI ntac r co -INTER o 8 1-88 (R) HI1106 8-Bit, 35 MSPS, Speed D/A Converter (TTL Input) Description The HI1106 is an 8-bit, 35MHz, high-speed D/A converter IC. Summing type current for the upper 2 bits and ladder type resistance for the lower 6 bits, ensures a low power consumption of 200mW (single power supply). This IC is suitable for digital TVs, graphic displays and otherapplications. * Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-Bit * High Speed Operation . . . . . . . . . . . . . . . . . . . . . 35MHz (Maximum Conversion Speed) * Non-Linearity . . . . . . . . . . . . . . . . . Less Than 1/2 LSB * Low Glitch * TTL Compatible Input * Power Supply - Single . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V - Dual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V * Low Power Consumption - +5V Single Power Supply (Typ) . . . . . . . . . . 200mW - 5V Dual Power Supply (Typ) . . . . . . . . . . . . 400mW * Direct Replacement for the Sony CXA1106 Ordering Information PART NUMBER HI1106JCB HI1106JCP TEMP. RANGE (oC) -20 to 75 -20 to 75 PACKAGE 24 Ld SOIC 24 Ld PDIP PKG. NO. M24.2-S E24.4-S Pinout HI1106 (PDIP, SOIC) TOP VIEW VREF 1 AGND1 2 AGND2 3 AOUT 4 DGND2 5 VCC 6 DGND1 7 NC 8 CLK 9 D7 (MSB) 10 NC 11 D6 12 24 VSET 23 VEE 22 NC 21 NC 20 D0 (LSB) 19 D1 18 D2 17 D3 16 D4 15 D5 14 NC 13 NC CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved 10-1 File Number 4113.3 HI1106 Functional Block Diagram DGND2 5 23 VEE DECODER CLOCK SYNCHRONIZED CIRCUIT D7 10 (MSB) D6 12 INPUT BUFFER D5 15 DIGITAL DATA INPUT D4 16 D3 17 D2 18 D1 19 D0 20 (LSB) CLOCK BUFFER 2 4 3 CURRENT SWITCH R R R R R R R 2R 2R 2R 2R 2R R 2 AGND1 INTERNAL REFERENCE VOLTAGE 1 VREF 3 AGND2 AOUT ANALOG OUTPUT 3 6 6 VCC 6 -+ 9 7 24 VSET CLK DGND1 Pin Descriptions PIN NO. 1 SYMBOL VREF AGND1 2 EQUIVALENT CIRCUIT DESCRIPTION Internal Reference Voltage Output pin 1.2V (Typ). An external pull down resistance is necessary. For reference see Notes on Application 1. AGND2 1 VEE 23 2 AGND1 Set to Analog VCC for signal power supply and to Analog GND for dual power supply. Connect to AGND2 and use. Connect to AGND1. Analog Output pin. AGND2 3 RO 4 3 4 AGND2 AOUT VEE 23 5 6 7 DGND2 VCC DGND1 Set to Digital VCC for signal power supply and to Digital GND for dual power supply. Digital VCC . Digital GND. 10-2 HI1106 Pin Descriptions PIN NO. 8 9 SYMBOL NC CLK VCC 6 (Continued) EQUIVALENT CIRCUIT No Connect. Clock Input pin. DESCRIPTION 9 DGND1 7 10, 12, 15 - 20 D7, D6, D5 - D0 Digital Input pin. D1 to MSB, D8 to LSB VCC 6 10, 12 15 TO 20 DGND1 7 11, 13, 14 21, 22 23 24 NC NC VEE VSET No Connect Connect to AGND or VEE . Set to Analog GND for single power supply and to VEE for dual power supply. AGND1 2 Bias Input pin. Normally set VSET - VEE to 0.84V. For reference see Notes on Application 1. 24 VEE 23 NOTE: See the Application Circuit for reference. 10-3 HI1106 Absolute Maximum Ratings TA = 25oC Supply Voltage VCC - DGND1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 6V VEE - AGND1, AGND2 . . . . . . . . . . . . . . . . . . . . . . . . . . -6V to 0V DGND2 - DGND1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 6V Digital Input Voltage VI . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND1 - 0.3V to VCC + 0.3V VCLK . . . . . . . . . . . . . . . . . . . . . . . . DGND1 - 0.3V to VCC + 0.3V Input Voltage (V SET Pin), VSET . . . . . . . . VEE - 0.3V to VEE + 2.7V Output Current (V REF Pin), lREF . . . . . . . . . . . . . . . . . -5mA to 0mA Thermal Information Thermal Resistance (Typical, Note 2) JA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Maximum Power Dissipation, PD . . . . . . . . . . . . . . . . . . . . . . 1.27W Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range, TSTG . . . . -55oC to 150oC Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Recommended Operating Conditions SINGLE POWER SUPPLY MIN TYP MAX Supply Voltage VCC, DGND2, AGND1, AGND2 . . . . . . . . 4.75V 5V 5.25V DGND2 - AGND1, DGND2 - AGND2 . . . . -0.2V 0V 0.2V AGND1 - AGND2 . . . . . . . . . . . . . . . . . . . -0.1V 0V 0.1V Digital Input Voltage H Level, VIH, VCLKH . . . . . . . . . . . . . . . . . 2.0V VCC L Level, VIL, VCLKL . . . . . . . . . . . . . . . . . .DGND1 1V VSET Input Voltage, VSET . . . . . . . . . . . . . . 0.70V 0.84V 1V VREF Pin Current, IREF . . . . . . . . . . . . . . . .-3.0mA -0.4mA Clock Pulse Width (Note 1) tPW1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ns tPW0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ns Temperature Range, TOPR . . . . . . . . . . . . . . . . . . . . -20oC to 75oC DUAL POWER SUPPLY Supply Voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND2 - AGND1, DGND2 - AGND2 . . . AGND1 - AGND2. . . . . . . . . . . . . . . . . . . Digital Input Voltage H Level, VIH , VCLKH . . . . . . . . . . . . . . . . L Level, VIL , VCLKL . . . . . . . . . . . . . . . . . VSET Input Voltage, VSET. . . . . . . . . . . . . . VREF Pin Current, IREF. . . . . . . . . . . . . . . . Clock Pulse Width tPW1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . tPW0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . MIN 4.75V -5.5V -0.2V -0.1V TYP 5V 5V 0V 0V MAX 5.25V -4.75V -0.2V 0.1V 2.0V VCC DGND1 1V -4.30V -4.16V -4.00V -3mA -0.4mA 10ns 10ns - CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. See Figure 6 in the Timing Diagram. 2. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications PARAMETER SINGLE POWER SUPPLY Resolution, n Maximum Conversion Speed, fMAX Linearity Error, EL Differential Linearity Error, ED Full Scale Output Voltage, VFS Offset Voltage (Note 2), VOS Output Resistance, RO Power Supply Current, ICC Digital Input Current H Level, IIH L Level, IIL VSET Input Current, ISET TA = 25oC, VCC = DGND2 = AGND1 = AGND2 = 5V, DGND1 = VEE = 0V, VSET = 0.84V TEST CONDITIONS MIN RL > 10k, CL < 20pF RL > 10k RL > 10k RL > 10k RL > 10k, IREF = -400A 35 -0.5 -0.5 0.9 0 290 32 0 -400 -3 IREF = -400A RL > 10k 1.17 0.5 10 2 RL > 10k RL > 10k, fCLK = 1MHz, Digital Lamp Output TYP 8 1.0 4 350 40 1.25 1.0 11 30 MAX 0.5 0.5 1.1 10 410 48 5 0 0 1.33 1.50 UNIT Bit MHz LSB LSB V mV mA A A A V V ns ns ns pV/s Internal Reference Output Voltage, VREF Accuracy Output Voltage Range, VOC Set-Up Time, tS Hold Time, tH Propagation Delay Time, tPD Glitch Energy, GE NOTE: 3. V OS = AGND2 - V255 (V255 is the output voltage when full input is at high level). 10-4 HI1106 Electrical Specifications PARAMETER DUAL POWER SUPPLY Resolution, n Maximum Conversion Speed, fMAX Linearity Error, EL Differential Linearity Error, DNL Full Scale Output Voltage, VFS Offset Voltage, VOS Output Resistance, RO Power Supply Current ICC IEE Digital Input Current H Level, IIH L Level, IIL VSET Input Current, ISET Internal Reference Output Voltage, VREF Accuracy Output Voltage Range, VOC Set-Up Time, tS Hold Time, tH Propagation Delay Time, tPD Glitch Energy, GE RL > 10k RL > 10k, fCLK = 1MHz Digital Lamp Output INPUT/OUTPUT CODE TABLE (When Output Full Scale Voltage at 1.00V) INPUT CODE MSB 1 1 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 LSB 1 0 0 OUTPUT VOLTAGE (SINGLE SUPPLY) VCC V CC -0.5V VCC -1V OUTPUT VOLTAGE (DUAL SUPPLY) -0V -0.5V -1V IREF = -400A RL > 10k 0 -400 -3 -3.83 0.5 10 2 -3.75 1.0 11 30 5 0 0 -3.67 1.50 A A A V V ns ns ns pV/s RL > 10k, IREF = -400A 24 40 30 50 36 60 mA mA RL > 10k RL > 10k RL > 10k, CL < 20pF RL > 10k 35 -0.5 -0.5 0.9 0 290 8 1.0 4 350 0.5 0.5 1.1 10 410 Bit MHz LSB LSB V mV TA = 25oC, VCC = 5V, DGND1 = DGND2 = AGND1 = AGND2 = 0V, VEE = -5V, VSET - VEE = 0.84V TEST CONDITIONS MIN TYP MAX UNIT 10-5 HI1106 Test Circuits (MSB) D7 D6 D5 10 12 15 HI1106 2 (LSB) D0 VCC DGND1 CLK TTL LEVEL 20 6 7 9 4 5 AOUT DGND2 3 AGND1 AGND2 V 1 24 23 VREF VSET 0.47 VEE V 3K CLK SINGLE POWER SUPPLY DUAL POWER SUPPLY DVCC AVCC DGND AGND VEE FIGURE 1. DC CHARACTERISTICS (MSB) D7 D6 10 12 15 1 24 23 VREF VSET 0.47 VEE 3K V 8-BIT COUNTER (TTL LATCH OUTPUT) D5 HI1106 (LSB) D0 VCC DGND1 20 6 7 9 2 3 AGND1 AGND2 DIGITAL LAMP WAVEFORM OCCURRENCE OSCILLOSCOPE RIN = 1M CIN = 10pF BW = 20MHz 4 5 AOUT DGND2 CLK CLK 35MHz TTL LEVEL SQUARE WAVEFORM CLK SINGLE POWER SUPPLY DUAL POWER SUPPLY 2ns TO 14ns DATA DVCC AVCC DGND AGND VEE TIMING BETWEEN CLK AND DATA FIGURE 2. MAXIMUM CONVERSION SPEED 10-6 HI1106 Test Circuits (Continued) VREF VSET 0.47 VEE V 3K (MSB) D7 D6 10 12 15 1 24 23 8-BIT COUNTER (TTL LATCH OUTPUT) (LSB) D5 HI1106 D0 VCC DGND1 20 6 7 9 2 3 AGND1 AGND2 DIGITAL LAMP WAVEFORM OCCURRENCE OSCILLOSCOPE RIN = 1M CIN = 20pF BW = 5MHz PULSE GENERATOR 1MHz TTL 4 5 AOUT DGND2 CLK DELAY CONTROLLING PULSE GENERATOR 1MHz TTL FET PROBE FET PROBE OSCILLOSCOPE RIN = 50 CIN = 10pF BW = 200MHz SINGLE POWER SUPPLY DUAL POWER SUPPLY DVCC AVCC DGND AGND VEE FIGURE 3. SET-UP TIME AND HOLD TIME 10-7 HI1106 Test Circuits (Continued) (MSB) D7 D6 10 12 15 1 24 23 VREF VSET 0.47 VEE V 3K 8-BIT COUNTER (TTL LATCH OUTPUT) D5 HI1106 (LSB) D0 VCC DGND1 20 6 7 9 2 3 AGND1 AGND2 DIGITAL LAMP WAVEFORM OCCURRENCE OSCILLOSCOPE RIN = 1M CIN = 10pF BW =5MHz 4 5 AOUT DGND2 CLK CLK 1MHz TTL LEVEL SQUARE WAVEFORM CLK SINGLE POWER SUPPLY DUAL POWER SUPPLY 2ns TO 90ns DATA DVCC AVCC DGND AGND VEE TIMING BETWEEN CLK AND DATA FIGURE 4. GLITCH AREA 10-8 HI1106 Test Circuits (Continued) D7 D6 D5 10 12 15 1 24 23 VREF VSET 0.47 VEE 3K V 1/ DIVIDER 2 HI1106 D0 VCC DGND1 20 6 7 9 2 3 AGND1 AGND2 5 4 DGND2 AOUT FET PROBE FET PROBE OSCILLOSCOPE RIN = 50 CIN = 10pF BW = 200MHz CLK CLK 10MHz TTL LEVEL SQUARE WAVEFORM SINGLE POWER SUPPLY DUAL POWER SUPPLY CLK 2ns TO 90ns DVCC AVCC DGND AGND VEE DATA TIMING BETWEEN CLK AND DATA FIGURE 5. PROPAGATION DELAY TIME 10-9 HI1106 Timing Diagram tPW1 tPW0 CLK tS tH DATA tS tH tS tH VTH = 1.5V VTH = 1.5V tPD 100% D/AOUT tPD tPD 50% 0% FIGURE 6. Typical Performance Curves TA = 25oC VCC = DGND2 = AGND1 = AGND2 = 5V DGND1 = VEE = 0 RL > 10k 2.0 TA = 25 oC VCC = 5V DGND1 = DGND2 = AGND1 = AGND2 = 0 VEE = -5V RL > 10k 2.0 VFS (V) VFS (V) RL = 330 1.0 RL = 330 1.0 0 1.0 VSET (V) 2.0 0 1.0 VSET - VEE (V) 2.0 FIGURE 7. FULL-SCALE OUTPUT VOLTAGE (VFS) vs VSET (SINGLE POWER SUPPLY) FIGURE 8. FULL-SCALE OUTPUT VOLTAGE (VFS) vs VSET - VEE (DUAL POWER SUPPLY) 10-10 HI1106 Typical Performance Curves (Continued) 1.02 TA - VFS / VFS (25oC) TA - VFS / VFS (25oC) 1.02 1.00 VSET = 0.84V IREF = -400A VCC = DGND2 = AGND1 = AGND2 = 5V DGND1 = VEE = 0 RL 10k 0 20 40 60 80 TA , AMBIENT TEMPERATURE (oC) 1.00 VSET - VEE = 0.84V IREF = -400A VCC = 5V DGND1 = DGND2 = AGND1 = AGND2 = 0V VEE = -5V RL 10k 0 20 40 60 80 0.98 0.98 0.96 0.96 -20 -20 TA , AMBIENT TEMPERATURE (oC) FIGURE 9. FULL-SCALE OUTPUT VOLTAGE (VFS) vs TEMPERATURE (SINGLE POWER SUPPLY) FIGURE 10. FULL-SCALE OUTPUT VOLTAGE (VFS) vs TEMPERATURE (DUAL POWER SUPPLY) 3.0 3.0 2.5 2.5 VOS (mV) VOS (mV) 2.0 2.0 VSET - VEE = 0.84V IREF = -400A VCC = 5V DGND1 = DGND2 = AGND1 = AGND2 = 0V VEE = -5V RL 10k 0 20 40 60 TA , AMBIENT TEMPERATURE (oC) 80 1.5 1.0 VSET = 0.84V IREF = -400A VCC = DGND2 = AGND1 = AGND2 = 5V DGND1 = VEE = 0V RL 10k 0 20 40 60 80 TA , AMBIENT TEMPERATURE (oC) 1.5 1.0 -20 -20 FIGURE 11. OUTPUT OFFSET VOLTAGE (VOS) vs TEMPERATURE (SINGLE POWER SUPPLY) FIGURE 12. OUTPUT OFFSET VOLTAGE (VOS) vs TEMPERATURE (DUAL POWER SUPPLY) 10-11 HI1106 Typical Performance Curves IREF = -400A VCC = DGND2 = AGND1 AGND2 = 5V DGND1 = VEE = 0V VREF (V) (Continued) IREF = -400A VCC = 5V 1.260 DGND1 = DGND2 = AGND1 = AGND2 = 0V VEE = -5V 1.260 VREF (V) 1.250 1.250 1.240 1.240 1.230 1.230 -20 0 20 40 60 80 -20 0 20 40 60 80 TA , AMBIENT TEMPERATURE (oC) TA , AMBIENT TEMPERATURE (oC) FIGURE 13. INTERNAL REFERENCE VOLTAGE (V REF) vs TEMPERATURE (SINGLE POWER SUPPLY) FIGURE 14. INTERNAL REFERENCE VOLTAGE (V REF) vs TEMPERATURE (DUAL POWER SUPPLY) 2.0 VTH (V) VCC = DGND2 = AGND1 = AGND2 = 5V DGND1 = VEE = 0V 2.0 VCC = 5V DGND1 = DGND2 = AGND1 = AGND2 = 0V VEE = -5V 1.0 VTH (V) 1.5 0 20 40 60 80 -20 -20 0 20 40 60 80 TA , AMBIENT TEMPERATURE (oC) TA , AMBIENT TEMPERATURE (oC) FIGURE 15. THRESHOLD VOLTAGE (VTH) OF DIGITAL INPUT vs TEMPERATURE (SINGLE POWER SUPPLY) FIGURE 16. THRESHOLD VOLTAGE (VTH) OF DIGITAL INPUT vs TEMPERATURE (DUAL POWER SUPPLY) 1.050 3 VOS (V) TA = 25 oC VSET = 0.84V VCC = DGND2 = AGND1 = AGND2 DGND1 = VEE = 0V RL 10k 4.5 5.0 VCC (V) 5.5 VFS (V) 1.000 TA = 25oC VSET = 0.84V VCC = DGND2 = AGND1 = AGND2 DGND1 = VEE = 0V RL 10k 5.0 VCC (V) 5.5 2 0.950 1 0.900 0.850 4.5 FIGURE 17. OUTPUT OFFSET VOLTAGE (VOS) vs SUPPLY VOLTAGE (SINGLE POWER SUPPLY) FIGURE 18. OUTPUT FULL-SCALE VOLTAGE (V FS) vs SUPPLY VOLTAGE (DUAL POWER SUPPLY) 10-12 Typical Performance Curves (Continued) 1.260 TA = 25 oC I REF = -400A VCC = DGND2 = AGND1 = AGND2 DGND1 = VEE = 0V VFS (V) 1.250 1.240 1.230 4.5 5.0 VCC (V) 5.5 FIGURE 19. INTERNAL REFERENCE VOLTAGE (VREF) vs SUPPLY VOLTAGE (SINGLE POWER SUPPLY) Application Circuits 13 8-BIT DIGITAL INPUT (TTL) D5 D4 D3 D2 D1 D0 NC NC VEE VSET 14 15 16 17 18 19 20 21 22 23 24 12 D6 D7 11 (MSB) 10 CLK 9 8 7 6 5 4 3 2 1 DGND1 VCC DGND2 AOUT AGND2 AGND1 VREF CLK (TTL) R LPF D/AOUT + MATCHING RESISTANCE FOR LPF 3K FIGURE 20. SINGLE POWER SUPPLY 10-13 Application Circuits 13 8-BIT DIGITAL INPUT (TTL) D5 D4 D3 D2 D1 D0 (LSB) NC NC VEE VSET 14 15 16 17 18 19 20 21 22 23 24 12 D6 D7 11 (MSB) 10 CLK 9 8 7 6 5 4 3 2 1 DGND1 VCC DGND2 AOUT AGND2 AGND1 VREF CLK (TTL) R + LPF D/A OUT MATCHING RESISTANCE FOR LPF 3K DVCC AVCC DGND AGND VEE FIGURE 21. DUAL POWER SUPPLY Notes On Application 1. Setting of VREF Pin (Pin 24) The full-scale voltage of the D/A output is determined by VSET input voltage. As about (1.2V - VEE) DC voltage is generated at VREF pin (Pin 1) by connecting an external resistor from VREF pin to VEE pin (Pin 23), divide this voltage using resistors and apply it to VSET pin as Figure 22. Example of usage: IREF 2. Phase Relation Between Data and Clock To make the best use of the inherent characteristics of this D/A converter the phase relation between the data and clock applied from the exterior, should be properly set. Set up time (tS) and Hold time (tH ) should be as indicated in the Electrical Specifications. For tS and tH refer to Figure 6 in the Timing Waveform. Also, set the clock pulse width according to the Recommended Operating Conditions. 3. D/A Output Pin Load Receive the D/A output stage at high impedance, so as to obtain: RL > 10k, CL < 20pF. 4. Noise Reduction Refer to the following notes in order to minimize noise contamination that occurs from outside the IC and penatrates D/A output. * The power supply line and ground line should be made as wide as possible when fixed to the printed circuit board. Analog and Digital circuits should be separated. * Connected a bypass capacitor between each of DVCC (Pin 6) and DGND1 (Pin 7); AGND1, 2 (Pins 2, 3) and VEE (Pin 23); VSET (Pin 24) and V EE (Pin 23), respectively. 1 24 23 VREF VSET VEE R VSET SINGLE POWER SUPPLY DUAL POWER SUPPLY VEE AGND FIGURE 22. The full-scale voltage of the D/A output can be determined from the following equation: VFS = 1.2 (VSET - VEE) (RL > 10k, 0.4V VSET 1.2V Select an external resistor R (connected to VREF pin) so that IREF (current of an external resistor) is within the value indicated as the Recommended Operating Conditions of (-3mA < IREF < -0.4mA). 10-14 |
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